Utilizing proprietary patent pending ASIC acceleration technology, Anchiva's Secure Web Gateways (SWG) quickly and comprehensively detect and eliminate malicious code such as malware, viruses and spyware without affecting the performance of web based applications, being possible to be deployed into a large network environment.

 

Traditional hardware acceleration technology in security appliances focuse mainly at accelerating packet processing at the network layer rather than the application layer. This technology scans a small amount of transferring data, such as head of data link layer, network layer, and transmission layer, and no content in application layer is scanned.

 

As shown figure 1 below, the SWG architecture integrates the ASIC into the appliance design by way of a high-speed data communication bus without CPU occupation. As data is received at the interfaces of the SWG, AnchivaOS acts as a transparent proxy intercepting traffic that matches a policy. During this process, AnchivaOS uses its multi-core CPU's and ASIC engine to identify, reassemble and classify the content of the data.

 

Fig 1:

 

In the real network environment, malware signatures have a wide range of variety, so when a signature library is built, all the factors such as file types, offset addresses and wild cards are included in it, making the signature matching logic more and more complicated and time-consuming.

 

Anchiva's proprietary hardware scanning algorithm is illustrated in the flow diagram. When data are transmitted into ASIC accelerator's built-in data buffer, the signature parallel scanner starts working and matching basic signature library. Afterwards, the cleaned-up data flow passes through while suspicious traffic is sent to malware scanner for an exact matching. It only takes a small amount of time to execute both match filtering by parallel scanners at the first step and exact matching of malware scanner, which reduces scanning and matching time without having influence on the scanning result.

 

Fig 2:

For more information, please visit "ASIC Hardware Acceleration White Paper".